The present invention relates to a non-volatile memory semiconductor device and a method for manufacturing a non-volatile memory semiconductor device, and more particularly, to a non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer and a method for manufacturing a non-volatile memory semiconductor device having an ONO top dielectric layer.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing such an NVM memory cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and Electrically Erasable Programmable Read-Only Memory (EEPROM). Typically, NVM can be programmed with data, read and/or erased, and the programmed data can be stored for a long period of time prior to being erased, even as long as ten years.
Nitride read only memory (NROM) is a type of EEPROM that uses charge-trapping for data storage. An NROM cell is typically composed of a metal-oxide-silicon field effect transistor (MOSFET) having an ONO (oxide-nitride-oxide) layer disposed between the gate and the source/drain of the semiconductor material. The nitride layer in the ONO layer is able to “trap” charge (electrons) when the device is “programmed.” Charge localization is the ability of the nitride material to store the charge without significant lateral movement of the charge throughout the nitride layer. NROM utilizes a relatively thick tunnel oxide layer, which typically negatively impacts the time it takes to erase a memory cell. NROM can be contrasted with conventional “floating gate” memory cells wherein the floating gate is conductive and the charge is spread laterally throughout the entire floating gate and charge is transferred through a tunnel oxide layer. Programming (i.e. charge injection) of the charge-trapping layer in NROM cells can be carried out by various hot carrier injection methods such as channel hot electron injection (CHE), source side injection (SSI) or channel initiated secondary electron (CHISEL), which all inject electrons into the nitride layer. Erasing is performed by applying a positive gate voltage, which permits hole tunneling through the ONO top dielectric layer from the gate. Erasing (i.e., charge removal) in NROM devices is typically carried out by band-to-band hot hole tunneling (BTBHHT). However, BTBHHT erasing causes many reliability issues with NROM devices and causes degradation of the NROM devices and charge loss after many program/erase cycles. Reading is carried out in a forward or reverse direction. Localized charge-trapping technology allows two separate bits per cell, thus resulting in a doubling of memory density. The NROM can be repeatedly programmed, read, erased and/or reprogrammed by known voltage application techniques.
Another EEPROM is a metal-nitride-oxide-silicon (MNOS) memory cell as shown in FIG. 4B. A typical MNOS 40 includes a very thin layer of insulating material 50 like silicon dioxide (SiO2) to separate a silicon nitride charge storage region 54 from a gate 55 and from a well region 45 of the semiconductor device. An MNOS 40 also includes a substrate 41 in which a source 44 and a drain 42 are formed. The well region 45 is disposed between the source 44 and the drain 42 under the gate 55. Erasing an MNOS 40 includes injecting holes into the nitride region 54 from the gate 55. This is accomplished by using a large positive gate voltage while grounding the source 44, the drain 42 and the substrate 41. In order to facilitate hole injection from the gate 55, there is nothing between the nitride 54 and the gate 55. However, such MNOS devices 40 suffer from charge retention problems in the nitride region 54 because electrons can easily “de-trap” from the nitride region 54 into the gate 55.
Yet another EEPROM is a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. U.S. Pat. No. 6,011,725 (Eitan), the entire content of which is incorporated by reference herein, provides a detailed comparison of several of the prior art NVMs including respective programming, erasing and reading techniques. The Eitan patent also discloses a type of SONOS memory cell capable of storing two data bits by localized charge storage techniques.
A typical conventional SONOS device 10 is shown in FIG. 4A. The conventional SONOS device 10 includes a silicon substrate 11, a source 14, a drain 12, a well region 15 and a first oxide layer 20 on top of the well region 15 extending over portions of the source 14 and the drain 12. A nitride charge storage layer 24 is provided above the first oxide layer 20, and a second oxide layer 30 is provided above the nitride charge storage layer 24. A polysilicon (poly) gate 25 is disposed on top of the ONO stack 20, 24, 30. By providing the second oxide layer 30 on top of the nitride layer 24 there is an improvement in the ability to control where the charge is placed or stored within the nitride layer 24 during programming operations. Additionally, the addition of the second oxide layer 24 prevents holes from entering from the overlying gate 25. In order for electrons to be able to tunnel through the oxide layer 20, the oxide layer 20 must be relatively thin, e.g., 20-30 Angstroms (Å). However, direct tunneling at retention still occurs which causes unsatisfactory retention results.
It is desirable to provide a non-volatile memory semiconductor device that has improved charge retention compared to conventional SONOS and MNOS devices. It is desirable to provide a non-volatile memory semiconductor device having a band-gap engineered oxide-nitride-oxide (ONO) top dielectric layer which serves as a blocking oxide or top oxide layer. It is also desirable to provide a non-volatile memory which can be erased using gate-injected holes by applying a positive gate voltage.